Frequently
Asked Questions:
Devices/
Design:
What
is the difference between a custom and a semi-custom device?
What is the normal design flow?
How much digital circuitry can the 700 Series Bipolar
Analog Arrays fit?
How high/ low is the input impedance?
How low of a current can be measured with the 700
Series Arrays?
Where do I get information on sample circuits?
Can I do a DAC in the arrays?
How can I find out what kind of performance is possible
in the arrays?
Which 700 Series Bipolar Analog Array fits my design?
Is
there added noise in the circuitry due to the architecture of the
arrays?
What operating voltages do the arrays support?
How long is the design cycle for a 700 Series Bipolar
Analog Array?
What are the quick limitations of the arrays?
Simulation:
What
is Monte Carlo analysis?
How do I install SIMetrix support for the 700 Series
Bipolar Analog Arrays?
How
do I install the tools?
What if I want to view other files from SIMetrix
(such as other LVS files)?
Layout/
Breadboarding:
How
do I install the commands for ICED into SIMetrix?
How
can I make sure that my circuit will function in the arrays before
I build my design?
Frequently
Given Responses (Please excuse the in-process answers):
A custom device
or ASIC requires a full set of masks. Masks are like negatives that
define where the circuitry goes. This means that for a full CMOS
process, you need to buy a full set of masks, or about 16 different
masks. For a 0.18 micron process, this can cost as much as $500,000.
For a semi-custom, you only make masks for the metalization layers
to customize the device. All other layers are already there.
Normally, a
customer and DEI will colaborate on a specification for a chip.
Then, schematic capture is done to capture a representation of what
the circuitry will do. Simulations verify that the circuit will
operate over temperature and process variations (this is the reason
that DEI suggests the use of SIMetrix monte carlo analysis - to
simulate process variations of separate components). Breadboarding
of critical circuits will be completed in many instances of newer
schematics or changes.
Once this is
complete and the circuit is operational, layout is performed by
either DEI or yourself using ICED from IC Editors, Incorporated.
A GDSII, which is basically a Gerber file for an IC, is created
and sent to the fabrication facility to build a metal mask (one
mask only). Ceramic prototypes are back within three weeks.
In Monte Carlo
analysis, the parameters of components are varied independantly
to simulate process variations. There are typically two types of
process variations in semiconductors: process variations on a particular
wafer and process variations from run to run.
As an example,
a resistor in the Bipolar Analog Arrays will vary in its initial
tolerance by +/- 20%, however, any two resistors on the same die
differ by less than 2%. The Design Manual also shows that the variation
between several resistors ganged together will be less than 1% (between
10 resistors combined for one total resistance and 10 resistance
combined for another resistance).
Example:
Suppose you
have a resistor divider between two base resistors as shown (the
value "1" means one 750 ohm resistor.

The nominal
output at VOUT is 2.5V. The nominal output impedance is half of
the base resistance or 375 ohms. The tolerance on the output resistance
is +/- 20%, which results in a range from 300 ohms to 450 ohms (half
of 600 ohms to 900 ohms)! The good news is that the ratio will vary
by much less than that, or 2% matching. This gives an output voltage
of 2.45 volts to 2.55 volts. If at least ten resistors are used
to make up the two effective resistors, statistics will yield you
a 1% matching, or a variation from 2.475 volts to 2.525 volts.
To see this
variation, you must run a Monte Carlo analysis in addition to your
normal runs. Monte Carlo analysis will vary RB1 and RB2 separately,
giving you an output something like the following. This will show
you if your circuit will really work over process variations on
a given die. Note that it depends on how many runs you do as to
how close you will get to the actual variation. The circuit will
typically operate closer to a least means square type of rule than
linear variation.

An applications
note is coming soon. Information is also available in the Design
Manual. For a preliminary copy of the applications note, please
contact us. We can also provide applications
support.
An applications
note is coming soon. Information is also available in the Design
Manual. For a preliminary copy of the applications note, please
contact us. We can also provide applications support.
The Bipolar
Arrays can implement digital, but it is a small amount. An example
is a NAND gate as shown below. This circuit requires three transistor
sites (all three input transistors are in the same island) and 7
resistors. There could be a maximum of nine of these devices in
one 712 array.

The input impedance
can be set up to be either high or low. The high input impedance
would be on the scale of 100 K-ohms (darlington pair). For the low
input impedance application such as measuring a low current, the
input impedance can be on the order of 500 ohms.
To calculate
input impedance, use the following:
Input impedance
= Rpi = Beta/gm, where gm = Ic /(kT/q)
gm = Ic / (26
mV) at room temperature
We can measure
very low currents if necessary (around 1 uA or lower). In fact,
the lower the input current, the lower the operating current for
a differential stage, and the higher you need for input impedance.
In order to
measure a high input current and use low power techniques, the designer
can attenuate the input and run at lower currents.
Getting a quick
idea of which array to use is relatively easy. If you want, Device
Engineering Incorporated will size the design for you and give you
a price. We can also make an Excel Spreadsheet available with sizes
of some common circuits from the Design Manual in it. This will
allow you to make informed decisions.
One thing that
you must be aware of is the use of opamps. On a board, you use an
opamp with an "infinite" gain because semiconductor companies
can make these in volume and you can adjust the gain for your actual
needs. In an IC, you build a "gain stage" with just the
gain that you actually need. Since a gain stage is not a closed
loop device, your chances of oscillations are greatly decreased.
Also, an opamp takes between 14 and 20 transistor sites, while a
differential gain stage alone will take about 5 transistor sites.
So, for the fact of stability and size, it is usually better to
use a gain stage in an IC instead of an opamp with a couple of resistors.
Example circuits
and functions are available for download in a library format for
SIMetrix and for other formats. Please see our download page if
you want the actual schematics. A table is available in HTML format
that will tell you how many components these circuits will use.
Table
of Example Functions
Table
of Circuit Examples
The table of
circuit examples contains some full circuits and some examples on
how to acheive certain designs such as a Widlar current source.
Please see the
applications note TBD on this subject. If this appnote has not been
published yet, contact DEI and ask for tech support on arrays.
The best way
to estimate performance is to do a simulation. After that, it is
a good idea to do a breadboard with kit parts that are available
free of charge from Device Engineering. Since respins are also easier
than a full custom IC, your time can be spent where it is most important
- system level design.
Device Engineering
is working on a 5-bit DAC. This is the most bits acheivable with
1% matching. A 6-bit DAC would require better than 1% matching,
but we are trying some different techniques to make this happen.
No. This is
not a switched capacitor topology. The only noise sources are normal
noise sources for electronics.
0.9V to 20V
Simulation is
a great tool, but it is often not enough. Device Engineering offers
kit parts free of charge for prototyping circuits before they are
manufactured. Please see the list of kit
parts page.
The design cycle
is greatly reduced because of all of the circuits available as starting
points. Also, since the arrays are a single level of metal, the
time from when the layout is completed (GDSII generation which is
like a Gerber File) to the time where ceramic prototypes are ready
is three weeks. Plastic prototypes can be available in four weeks.
Ah, the Achiles
heel. The biggest limitation is the ability of the arrays to handle
higher voltages. The breakdown of the arrays is 20 V, which means
that you would do a supply of about 18V with a 10% tolerance as
an almost maximum. The only device that has a breakdown below 20V
is the capacitor, which has a breakdown of around 9 V.
The arrays are
capable of small amounts of digital, but as already mentioned, this
is limited.
Speeds are limited
for design. The NPN has an ft of 800 MHz, so for a gain of 20 dB,
you would need to be at least a decade in frequency away from this
point (80 MHz).
A semicustom
device is not designed for all applications, but when it fits an
application, it usually makes sense (and cents) since the NREs can
be much lower. The decrease in cycle time for getting to production
also decreases risk.
If you want
to add functionaility into the SIMetrix pull-down menus, you can
edit the icedmenu.txt file to add in a line. For instance, to be
able to open up other LVS files, you can add in the line:
DefMenu "Shell|&File|ICED
(for LVS)|View Results\other" "let resname=splitpath(getfile('Select
Result File To Edit\lvs'));if resname[0]='' then ;unlet resname;scriptabort;endif;shell
{'Notepad.exe '&resname[0]&resname[1]&resname[2]&resname[3]}"
"SchemOpen"
This should
go on all one line. What it does is:
- Defmenu defines
a new menu item, in the schell, under the ICED (for LVS) menu
as a View Results\other item.
- resname is
a variable to hold the value of the results file that you want
to see.
- splitpath
will ask you for the path to the file. Then it splits the path
into four parameters which are numbered 0 through 3. These are,
in order: the drive letter such as "C:", the directory
where the file exists, the file name, and the extension (with
a "." such as .LVS).
- Then, it
does a check to see if resname was defined or cancelled, and will
abort the script if necessary.
- shell will
run a command to open notepad with the file that you selected.
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